EDSEL=OFF, SOURCESEL=NONE
Channel Control Register
SIGSEL | Signal Select |
SOURCESEL | Source Select 0 (NONE): No source selected 1 (PRSL): Peripheral Reflex System 2 (PRSH): Peripheral Reflex System 8 (ADC0): Analog to Digital Converter 0 16 (USART0): Universal Synchronous/Asynchronous Receiver/Transmitter 0 17 (USART1): Universal Synchronous/Asynchronous Receiver/Transmitter 1 28 (TIMER0): Timer 0 29 (TIMER1): Timer 1 41 (RTCC): Real-Time Counter and Calendar 48 (GPIOL): General purpose Input/Output 49 (GPIOH): General purpose Input/Output 52 (LETIMER0): Low Energy Timer 0 60 (CRYOTIMER): CRYOTIMER 61 (CMU): Clock Management Unit 67 (CM4): undefined |
EDSEL | Edge Detect Select 0 (OFF): Signal is left as it is 1 (POSEDGE): A one HFCLK cycle pulse is generated for every positive edge of the incoming signal 2 (NEGEDGE): A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal 3 (BOTHEDGES): A one HFCLK clock cycle pulse is generated for every edge of the incoming signal |
STRETCH | Stretch Channel Output |
INV | Invert Channel |
ORPREV | Or Previous |
ANDNEXT | And Next |
ASYNC | Asynchronous Reflex |